Error correction in the computer storage using staircase codes

Purpose of research is to use non-binary staircase codes to correct errors that occur in the reading channels of external storage devices (ESD) of a computer.

Methods. Decoding of staircase codes is implemented by decoding words of component Reed-Solomon codes located in a pair of adjacent blocks in the decoding window. After decoding all the words of component codes, the data blocks in the window are shifted. Decoding of component code words in a window is performed in parallel, which reduces the delay of the staircase decoder. The procedure for decoding component Reed-Solomon codes involves the sequential execution of the following steps: 1) the syndrome polynomial is calculated; 2) polynomials of locators and error values are calculated (the key equation is solved); 3) the roots of the polynomial of error locators are sought; 4) error values are calculated; 5) erroneous symbols are corrected. To solve the key equation (step 2), it is proposed to use the ePIBMA (Enhanced Parallel Inversionless B-M Algorithm) algorithm.

Results. As a result of the study using computer simulation, the parameters of the staircase decoder were selected to optimize its operation: the number of half-iterations is 3; the decoding window size is 8 blocks; decoding delay is 6 blocks. For these parameters, the correction ability of the staircase decoder is close to maximum, with moderate complexity and latency. The effectiveness of staircase codes in the reading channels of the computer's ESD was studied using computer simulation. The percentage of blocks with uncorrectable errors was used as an indicator of efficiency. To take into account the grouping of errors symbols of ESD disk drives, a binary symmetric channel with memory (BSMC), which was described by a modified Bennett-Froelich model, was used as a channel model. The geometric distribution parameter g of this model was taken equal to 0.2, 0.5 and 0.9. A staircase code with component Reed-Solomon codes (224, 210, 15) defined over the GF(28) field was studied. Moreover, the speed of this staircase code is R = 0.87, which corresponds to the speed of the product of Reed-Solomon codes used in DVD optical discs. It is shown that when using code constructions with the same speed, the ratio of blocks with uncorrectable errors is smaller in the staircase code compared to the product of Reed-Solomon codes and that with increasing average error packet length this ratio decreases.

Conclusion. In the presented paper, it is proposed to use staircase codes with component Reed-Solomon codes to correct errors in the ESD of a computer with a sector organization. Decoding of these codes using the ePIBMA algorithm is considered. Using simulation, the parameters of the staircase code decoder were selected. The efficiency of error correction in channels with error grouping has been studied. The results of the study showed higher efficiency of staircase codes in channels with error grouping compared to a product of Reed-Solomon codes with the same redundancy

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